Allowed R6 · Within policy
{
"slug": "register-field-update",
"title": "Register Field Update",
"difficulty": "easy",
"tags": [
"coding",
"embedded",
"technical"
],
"is_free": true,
"locked": false,
"frequency": 1,
"last_reported_at": "2026-05-06T15:55:06.589300Z",
"url": "https://www.mokabla.com/en/c/valeo/register-field-update",
"agent": {
"page": "https://www.mokabla.com/agent/en/c/valeo/register-field-update",
"question": "https://www.mokabla.com/agent/_call/get_question?company=valeo&question=register-field-update"
},
"company": {
"slug": "valeo",
"name_en": "Valeo"
},
"body_md": "## Problem\nA 32-bit peripheral register packs several fields. Write `setField(reg, pos, width, value)` that returns the register with the `width`-bit field starting at bit `pos` replaced by `value`, leaving every other bit untouched, and `getField(reg, pos, width)` that reads it back. Then we talk about the C version: `volatile`, why read-modify-write is not atomic, and what an interrupt in the middle does to you.\n\n## Examples\n**Example 1**, `reg = 0xFFFF_FFFF`, set field `pos = 8`, `width = 4` to `0x3`\nMask is `0xF00`. Result: `0xFFFF_F3FF`. `getField(result, 8, 4) = 3`.\n\n**Example 2**, `reg = 0x0000_0000`, set `pos = 30`, `width = 2` to `0b10` → `0x8000_0000`. Setting `pos = 30`, `width = 2` to `0b111` must be **rejected or truncated**; say which and why. Reading `getField(0x8000_0000, 30, 2)` returns `2`.\n\n## Constraints\n- `0 <= pos < 32`, `1 <= width <= 32 - pos`.\n- In C: `uint32_t` everywhere; shifting a 32-bit `1` by 31 is fine, by 32 is undefined behaviour; guard `width == 32`.\n- The hardware register is memory-mapped; show the `volatile` declaration and explain what the compiler would otherwise do with two consecutive writes.\n\n## What they look for\n`mask = ((1u << width) - 1) << pos; reg = (reg & ~mask) | ((value << pos) & mask)`. Handling `width == 32` without UB. `volatile uint32_t *` for the register so reads and writes are not merged or reordered by the compiler. The atomicity point: an ISR that touches the same register between your read and your write loses its update; fixes are a critical section, bit-banding on Cortex-M3/M4, or the separate SET/CLEAR registers many peripherals provide.",
"follow_ups_md": "- The peripheral has separate `SET` and `CLR` registers: rewrite without read-modify-write.\n- Bit-banding: what is it and which cores have it?\n- Write-1-to-clear status registers: why does `reg |= FLAG` clear other flags by accident?",
"access": "Question bodies are paid content: a person buys 30 days of access per company (200 EGP or 200 points) in the human app. Agents get titles, tags and difficulty; bodies only for free questions."
}